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  • 1.
    Andreasson, Daniel
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Inbyggda System.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Inbyggda System.
    Improving BE traffic QoS using GT slack in NoC Systems2005In: Proceedings of 23th IEEE Norchip Conference, 21 - 22 Nov, Oulu, Finland, 2005Conference paper (Refereed)
    Abstract [en]

    Recently, network on chip (NoC) architectures are being

    proposed for implementing multi-core systems for realtime

    multi-media applications. The communication

    traffic of those systems will be a mix of guaranteed

    throughput (GT) and best effort (BE) traffic. GT traffic

    not only lead to under-utilization of communication links

    and routers, but also leads to degradation of QoS

    parameters for BE traffic. We propose a dynamic routing

    scheme for reducing jitter in the latency of BE traffic

    affected by the GT traffic. Our results from modeling and

    simulation indicate that a significant improvement in

    jitter can be achieved.

  • 2.
    Andreasson, Daniel
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Inbyggda System.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Inbyggda System.
    On improving Best-Effort throughput by better utilization of Guaranteed-Throughput channels in an on-chip communication system2004In: Proceedings of the NORCHIP 2004 conference, Oslo, 2004Conference paper (Refereed)
    Abstract [en]

    It is possible to concurrently run multiple

    applications on IP-core based SoC built using Network

    on Chip (NoC) paradigm. Some applications require

    predictable and guaranteed on-chip communication

    performance. In this paper we propose a new approach

    for using underutilized reservation of guaranteed

    throughput (GT) traffic to improve the performance of

    best effort (BE) traffic. We have modeled our scheme for

    a mesh topology NoC on a simulation platform. The

    results show that the proposed scheme leads to

    significant improvement in BE performance.

  • 3.
    Andreasson, Daniel
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Inbyggda System.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Inbyggda System.
    Slack-Time Aware Routing in NoC Systems2005In: Proceedings of International Symposium of Circuits and Systems, May 23-26, Kobe, Japan, 2005Conference paper (Refereed)
    Abstract [en]

    Efficient routing schemes are essential if Network on

    Chip (NoC) architectures are to be used for implementing

    multi-core systems for real-time multi-media applications.

    These systems will be characterized by internal communication

    traffic which is a mix of traffic requiring guaranteed

    throughput (GT) and other traffic requiring some other QoS

    properties like latency and less packet drops. Communication

    resources are generally reserved for providing GT

    performance. In this paper we propose a dynamic scheme for

    improving packet drop probability of other traffic by

    intelligently utilizing the under-utilized reserved

    communication resources of GT traffic. We demonstrate the

    effectiveness of our scheme by simulation.

  • 4.
    Andreasson, Daniel
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Inbyggda System.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Inbyggda System.
    STAR: An Efficient Routing Strategy for NoC with Mixed QoS Requirements2006In: Special Workshop on Future Interconnects and Network on Chip, Munich, Germany, 2006Conference paper (Refereed)
  • 5.
    Badri, Shabanam
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Holsmark, Rickard
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Junction Based Routing: A Scalable Technique To Support Source Routing in Large NoC Platforms2012In: Proceedings of Network on Chip Architectures 2012, ACM Digital Library, ACM Digital Library, 2012, p. 45-50Conference paper (Refereed)
    Abstract [en]

    To support communication among hundreds of cores on a chip, on-chip communication must be well organized. In the embedded systems using such a chip, the communication patterns can be profiled off-line and routing can be well planned. Source routing has been shown to be suitable in such contexts. However, source routing has one serious drawback of overhead for storing the path information in header of every packet. This disadvantage becomes worse as the size of the network grows. In this paper we propose a technique, called Junction Based Routing (JBR), to remove this limitation. In the proposed technique, path information for only a few hops is stored in the packet header.

    With this information, either the packet reaches the destination, or  reaches a junction from where the path information for on-ward path is picked up. There are many interesting issues related to this approach. We discuss and solve two important issues related to JBR, namely, the required number of junctions and their positions and path computation for efficient deadlock-free routing. A simulator has been developed to evaluate the performance of JBR and compare it with simple source routing. We observe that JBR has slightly worse performance as compared to pure source routing for packets with large payload. But JBR has  potential of higher performance for packets with small payloads.

  • 6.
    Bengtsson, Tomas
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Jutman, Artur
    Tallinn Technical University.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Ubar, Raimund
    Tallinn Technical University.
    Delay testing of asynchronous NoC interconnects2005In: Mixed design of integrated circuits and systems, MIXDES 2005: proceedings of the 12th International conference, Kraków, Poland, 22-25 June 2005, 2005Conference paper (Refereed)
  • 7.
    Bengtsson, Tomas
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Jutman, Artur
    Tallinn Technical University.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Ubar, Raimund
    Tallinn Technical University.
    Peng, Zebo
    Linköping University.
    Analysis of a Test Method for Delay Faults in NoC Interconnects2006In: Proceedings of IEEE East-West Design & Test Workshop (EWDTW), Kharkov: Kharkov National University of Radio Electronics , 2006, p. 42-46Conference paper (Refereed)
  • 8.
    Bengtsson, Tomas
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Jutman, Artur
    Tallinn Technical University.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Ubar, Raimund
    Tallinn Technical University.
    Peng, Zebo
    Linköping University.
    Off-line Testing of Delay Faults in NoC Interconnects2006In: Proceedings: 9th EUROMICRO Conference on Digital System Design : architectures, methods, and tools : (DSD 2006), 30 August-1 September 2006, Cavtat near Dubrovnik, Crotia, 2006, p. 677-680Conference paper (Refereed)
    Abstract [en]

    Testing of high density SoCs operating at high clock speeds is an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when the chip works at normal operating speed. In this paper, we propose a methodology for at-speed testing of delay faults in links connecting two distinct clock domains in a SoC. We give an analytical analysis about the efficiency of this method. We also propose a simple digital hardware structure for the receiver end of the link under test to detect delay faults. It is possible to extend our method to combine it with functional testing of the link and adapt it for online testing

  • 9.
    Bengtsson, Tomas
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Jutman, Artur
    Tallinn Technical University.
    Ubar, Raimund
    Tallinn Technichal University.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    A method for crosstalk fault detection in on-chip buses2005In: NORCHIP: proceedings : Oulu, Finland, 21-22 November 2005, 2005, p. 285-288Conference paper (Refereed)
  • 10.
    Bengtsson, Tomas
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems.
    A Survey of High Level Test Generation: Methodologies and Fault Models2004Report (Other academic)
    Abstract [en]

    Test of electronic circuits for fabrication fault is important if the circuits should have reasonable quality. To make the development of complex circuits manageable, methods and computer tools that work on a high level of abstraction are required. Development of test methodologies have however been left behind the increase of abstraction level used for the design. There is a risk that testing aspects become a bottle neck in the development of complex circuits if the test methods fail to cope up with the abstraction level for the design methods.

    System on Chips is often used to implement complex systems. The methods to make test for those circuits consists of three main parts. First part is the development of test procedures for the cores, which is preferably made at high level of abstraction. This area includes fault modeling and test pattern generation at behavior level of abstraction or higher as well as design of extra logic for insertion to facilitate testing. The second part requires development of methods to test the interconnections among cores.

    The third part is to develop a test access mechanism which can be used to test the cores and interconnections within a SoC. This survey is about development of fault models and test pattern for testing of cores at higher level of abstraction than logic level. A promising architecture for the interconnection is the Network on Chip architecture in which cores are interconnected through a network of packet switched switches. Testing of these switches will be identical to testing of a core.

    Models of physical and fabrication faults are needed at higher levels of abstraction in order to be able to develop test patterns from functional or behavioral description of cores. Researchers have experienced that the stuck-at fault model works quite well at logic level. But no such fault model has been discovered at behavioral or higher level which is universally accepted. Several behavior level fault models have been proposed. One of the proposed models is the variable bit stuck-at fault model. This model has been derived from the logic level stuck-at fault model but it does not give adequate coverage of physical faults. Physical faults inside components, like arithmetic and logic units, cannot be modeled in this way. With the methods proposed so far, knowledge of the logic level implementation of the unit is needed to model such faults. In this survey, we describe three proposed classes of fault models - fault models derived from logic level stuck-at faults, operator mutation faults and physically induced faults.

    Testing at higher level of abstraction has a lot in common with software testing. The pattern generation methods can be classified into two main categories, namely, code oriented methods and fault oriented methods. Methods can also be classified into methods that use fault simulation for test pattern generation or use algorithmic approach for test pattern generation. These two classification approaches are orthogonal leading to four different categories of methods. We have tried to put existing approaches in this category. We also survey the experimental setups developed and used by various research groups for carrying out research in high level testing. Some very interesting conclusions can be drawn about the efficacy of various categories of test pattern generation methodologies for testing various types of systems at behavioral level. An interesting conclusion is that code oriented methods are not very effective for testing data dominated circuits at behavioral level.

    Approaches followed by five different research groups working in the area of high level testing is also summarized and compared. We feel that the hierarchical test pattern generation method, which works simultaneously on several levels of abstraction, to generate test patterns is the most promising of these methods. We also feel that new fault models need to be developed to make testing at higher level of abstraction achieve adequate coverage of physical faults and become practically useful.

  • 11.
    Bengtsson, Tomas
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Jutman, Artur
    Tallinn Technical University.
    Ubar, Raimund
    Tallinn Technical University.
    An improved method for delay fault testing of NoC interconnections2006In: Date 06 Friday Workshop notes of Special Workshop on Future Interconnects and Networks on Chip, 2006Conference paper (Refereed)
  • 12.
    Bengtsson, Tomas
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Peng, Zebo
    Linköping University.
    Application Area Specific System Level Fault Models: A Case Study with a Simple NoC Switch2006In: Third IEEE International Workshop on Electronic Design, Test and Applications: proceedings, 17-19 January 2006, Kuala Lumpur, Malaysia, Los Alamitos: IEEE Computer Society , 2006Conference paper (Refereed)
  • 13.
    Bengtsson, Tomas
    et al.
    Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems.
    Ubar, R.
    Jutman, Artur
    Peng, Zebo
    Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols2008In: IET Computers and Digital Techniques, ISSN 1751-8601, Vol. 2, no 6, p. 445-460Article in journal (Refereed)
  • 14.
    Bengtsson, Tomas
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Ubar, Raimund
    Tallinn Technichal University.
    Jutman, Artur
    Tallinn Technical University.
    Off-line Testing of Crosstalk Induced Glitch Faults in NoC Interconnects2006In: Norchip, Linköping, Sweden, 20-21 November 2006: proceedings, 2006, p. 221-226Conference paper (Refereed)
  • 15. Bertozzi, Davide
    et al.
    Kumar, ShashiJönköping University, School of Engineering, JTH, Computer and Electrical Engineering.Palesi, Maurizio
    Networks-on-Chip2007Collection (editor) (Other (popular science, discussion, etc.))
  • 16. Bertozzi, Davide
    et al.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Palesi, Maurizio
    Networks-on-Chip: Emerging Research Topics and Novel Ideas (Editorial)2007In: VLSI design (Print), ISSN 1065-514X, E-ISSN 1563-5171, Vol. 2007, p. ID: 26454-Article in journal (Other (popular science, discussion, etc.))
  • 17. Frazzetta, D.
    et al.
    Dimartino, G.
    Palesi, Maurizio
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Data-Och Electronik. Jönköping University, School of Engineering, JTH. Research area Embedded Systems.
    Catania, V.
    Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links2008In: 11th Euromicro Conference on Digital System Design (DSD 2008): Architectures, Methods and Tools, 2008, p. 18-25Conference paper (Refereed)
  • 18. Hillung, Emil
    et al.
    Holsmark, Rickard
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems.
    Modeling and Evaluation of a Shared Memory Design for a Mesh Topology NoC Architecture2005In: WMSCI '05, Orlando, USA, July 2005, 2005Conference paper (Other scientific)
    Abstract [en]

    One of the limitations of the current NOC architectures is their inability to provide efficient access mechanisms for on-chip or off-chip memories. It is expected that a large amount of memory will be required to support many cores on a NoC system. In this paper, we describe an efficient 3-level memory hierarchy suitable for NoC based systems. We also present a design of the memory network interface to connect a shared memory core to an on-chip network for block based accesses. We have developed a model of a mesh topology NoC architecture of size 5x5 with a single shared on-chip memory and buffer-less routers. The routers implement a very simple adaptive routing scheme. In the model five cores are made to concurrently access the shared memory for blocks of data. We have carried out interesting experiments to study the variation of average memory access time for different network loads, block size and width of a channel connecting two routers. As expected the average access time improves with the increase in the block size due to pipelined nature of memory accesses through the network. The results show that the average access time of the shared memory could be acceptable for block sizes larger than 100 bytes with channel widths of 64 bits even when the other traffic load is as much as 80%. However, it will be very slow to access blocks smaller than 32 bytes from a shared memory.

  • 19.
    Holsmark, Rickard
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Embedded Systems.
    Högberg, Magnus
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Embedded Systems.
    Modelling and Evaluation of a Network on Chip Architecture using SDL2003In: 11th International SDL Forum Stuttgart, Germany, July 1-4, 2003, 2003Conference paper (Refereed)
    Abstract [en]

    Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication among cores. NoC paradigm provides the required scalability and reusability to reduce design time of SoCs. A NoC simulator is an important tool required to support development of designs based on a NoC architecture. In this paper, we describe the design of such a simulator using System Description Language (SDL). Features of SDL for representing structural hierarchy using blocks, concurrent processes and dynamic generation of processes, communication channels of user defined data types and timers are useful for modelling a NoC architecture at various levels of communication protocols. We use an event driven SDL simulator to carry out interesting experiments to evaluate various architectural options like buffer size in switches, and their effect on the performance like delay and packet loss.

  • 20.
    Holsmark, Rickard
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems.
    Johansson, Alf
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems.
    On Connecting Cores to Packet Switched On-Chip Networks: A Case Study with MicroBlaze Processor Cores2004In: 7th IEEE Workshop DDECS 04, Slovakia, 18-21 April, 2004, 2004Conference paper (Refereed)
    Abstract [en]

    The idea of using on chip packet switched networks for interconnecting a large number of IP cores is very practical for designing complex SoCs since it gives possibility of not only reusing IP cores but also the interconnection infrastructure. However, the real effort and time in using these Networks on Chip (NoC) goes in developing interfaces for connecting cores to the on-chip network. Standardization of interfaces for these cores can speed up the development process. In this paper, we present our work of developing an interface for a standard bus called OPB to the on-chip network. Any cores having OPB as the wrapper can reuse this interface. The paper also describes implementation of a small NoC prototype using this idea on an FPGA platform. The performance measurements on the prototype not only demonstrate the feasibility of NoC implementation but also demonstrate that FPGA based NoC implementation will be able to meet the performance requirements in many application areas. Specifically, we show that a core can communicate 2.5 MPackets/sec to a neighboring core.

  • 21.
    Holsmark, Rickard
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Embedded Systems.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Embedded Systems.
    Corrections to Chen and Chui's Fault Tolerant Routing Algorithm for Mesh Networks2007In: Journal of information science and engineering, ISSN 1016-2364, Vol. 23, no 6, p. 1649-1662Article in journal (Other (popular science, discussion, etc.))
    Abstract [en]

    Chen and Chiu published a fault tolerant routing algorithm for mesh topology net-works which they claimed was deadlock free in the presence of multiple faults. In this paper we give a counter-example to show that their Message-Route algorithm fails to provide deadlock free routing in a 2 dimensional mesh network. We also point out certain cases where the algorithm fails to route messages to their destinations. We identify an error in the proof of the main theorem in their paper which was used for proving the property of deadlock freeness. Changes to their algorithm are proposed to make it deadlock free and complete. We also discuss a new application of fault tolerant routing algorithms for non-homogeneous 2-dimensional mesh topology networks for on-chip communication.

  • 22.
    Holsmark, Rickard
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems.
    Design Issues and Performance Evaluation of Mesh NoC with Regions2005In: 23rd Norchip Conference, Oulu, Finland, November 2005, 2005Conference paper (Refereed)
    Abstract [en]

    Mesh topology is popular for Network on Chip (NoC) architectures because it has many desirable fabrication and performance properties, due to fixed sized rectangular tiles for resources. Region concept has been proposed to handle cores with larger size than the tiles. In this paper, we present an elaboration of the region concept, pointing out new design issues and possibilities. Special routing algorithms are required for deadlock free communication to handle blockage introduced by the regions. We show that fault tolerant algorithms developed for multi-computer systems can be adapted for this purpose. By simulation, we study the introduction of rectangular regions in a 7X7 NoC. Our study shows that the position and orientation of regions have a strong influence on achieved network performance.

  • 23.
    Holsmark, Rickard
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems.
    On options for accessing region in NoC2006In: Special Workshop on Future Interconnects and Network on Chip,10th March, 2006, Munich, Germany, 2006Conference paper (Other scientific)
  • 24.
    Holsmark, Rickard
    et al.
    Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems.
    Processor evaluation cube: A classification and survey of processor evaluation techniques2004Report (Other academic)
    Abstract [en]

    Selecting appropriate hardware resources corresponding to the application is an important task for design of an embedded system or a SoC. A large number of techniques have been proposed in literature to select a processor matching with the application requirements. In this report, we propose a framework called Processor Evaluation Cube (PEC) which helps in systematic classification and comparison of various processor evaluation techniques. The three axes of PEC are: Analysis, Architecture and Abstraction. The Analysis axis distinguishes methods employing static analysis or simulation; Architecture axis distinguishes methods evaluating single processor or multiprocessor computing platforms; Abstraction axis distinguishes methods employing clock true evaluation or higher level execution time estimation techniques. Our survey not only puts the existing techniques in proper perspective but also points to the weaknesses in the existing techniques which need to be removed if these techniques have to be used for design of multi-processor SoC (System on Chip) and Network on Chip (NoC) systems. We observe during our survey that the techniques for single processor evaluation are getting adapted for evaluation of multiprocessor platforms. We also note that there are no techniques developed or proposed for low level static analysis of multi-processor platforms due to complexity of such an evaluation. Although many different evaluation approaches may fall in the same category in PEC classification they have significant differences in intermediate descriptions of application, architecture and performance parameters.

  • 25.
    Holsmark, Rickard
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Palesi, Maurizio
    DIIT,University of Catania, Italy.
    A Multi-Level Routing Scheme and Router Architecture to support Hierarchical Routing in Large Network on Chip Platforms2010In: 4th Workshop on Highly Parallel Processing on a Chip (HPPC 2010), 2010Conference paper (Refereed)
    Abstract [en]

    The concept of hierarchical networks is useful for designing a large heterogeneous NoC by reusing predesigned small NoCs as subnets. It can also be helpful when analyzing and designing a large NoC as interconnection of subnets at a higher level of abstraction. Hierarchical deadlock-free routing is required to enable deadlock-free interconnection of sub-networks with different internal routing algorithms. In this paper we show that multi-level addressing is a cost-effective implementation option for hierarchical deadlock-free routing. We propose a two-level routing scheme, which is not only efficient, but also  enables co-existence of algorithmic and table-based implementation in one router. A hierarchical view of the network simplifies addressing of network nodes and address decoding in the router. Synthesis results show that a 2-level hierarchical router design for an 8x8 NoC, can reduce area and power requirements by  up to ~20%, as compared to a router for the flat network. This work also proposes a new possibility for increasing the number of nodes available for subnet-to-subnet interfaces, while keeping the properties of hierarchical deadlock-freedom. We evaluate and discuss the communication performance in a 2-level hierarchical network for various subnet interface set-ups and traffic situations. A cycle accurate simulator has been developed and used for this purpose.

  • 26.
    Holsmark, Rickard
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems.
    kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems.
    Palesi, Maurizio
    University of Catania, Italy.
    Mejia, Andres
    Technical University of Valencia, Spain.
    HiRA: A methodology for deadlock free routing in hierarchical networks on chip2009In: Networks-on-Chip, 2009. NoCS 2009. 3rd ACM/IEEE International Symposium on, IEEE Computer Society , 2009, p. 2-11Conference paper (Refereed)
    Abstract [en]

    Complexity of designing large and complex NoCs can be reduced/managed by using the concept of hierarchical networks. In this paper, we propose a methodology for design of deadlock free routing algorithms for hierarchical networks, by combining routing algorithms of component subnets. Specifically, our methodology ensures reachability and deadlock freedom for the complete network if routing algorithms for subnets are deadlock free. We evaluate and compare the performance of hierarchical routing algorithms designed using our methodology with routing algorithms for corresponding flat networks. We show that hierarchical routing, combining best routing algorithm for each subnet, has a potential for providing better performance than using any single routing algorithm. This is observed for both synthetic as well as traffic from real applications. We also demonstrate, by measuring jitter in throughput, that hierarchical routing algorithms leads to smoother flow of network traffic. A router architecture that supports scalable table-based routing is briefly outlined.

  • 27.
    Holsmark, Rickard
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Embedded Systems.
    Palesi, Maurizio
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Embedded Systems.
    Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions2008In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 54, no 3-4, p. 427-440Article in journal (Refereed)
    Abstract [en]

    The simplicity of regular mesh topology NoC architecture leads to reductions in design time and manufacturing cost. A weakness of the regular shaped architecture is its inability to efficiently support cores of different sizes. A proposed way in literature to deal with this is to utilize the region concept, which helps to accommodate cores larger than the tile size in mesh topology NoC architectures. Region concept offers many new opportunities for NoC design, as well as provides new design issues and challenges. One of the most important among these is the design of an efficient deadlock free routing algorithm. Available adaptive routing algorithms developed for regular mesh topology can not ensure freedom from deadlocks. In this paper, we list and discuss many new design issues which need to be handled for designing NoC systems incorporating cores larger than the tile size. We also present and compare two deadlock free routing algorithms for mesh topology NoC with regions. The idea of the first algorithm is borrowed from the area of fault tolerant networks, where a network topology is rendered irregular due to faults in routers or links, and is adapted for the new context. We compare this with an algorithm designed using a methodology for design of application specific routing algorithms for communication networks. The application specific routing algorithm tries to maximize adaptivity by using static and dynamic communication requirements of the application. Our study shows that the application specific routing algorithm not only provides much higher adaptivity, but also superior performance as compared to the other algorithm in all traffic cases. But this higher performance for the second algorithm comes at a higher area cost for implementing network routers.

  • 28.
    Holsmark, Rickard
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems.
    Palesi, Maurizio
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems.
    Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions2006In: 9th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools. Croatia, Sept 2006, 2006Conference paper (Refereed)
    Abstract [en]

    Region concept helps to accommodate cores larger than the tile size in mesh topology NoC architectures. In addition, it offers many new opportunities for NoC design, as well as provides new design issues and challenges. The most important among these is the design of a deadlock free routing algorithm. In this paper, we present and compare two routing algorithms for mesh topology NoC with regions. The first algorithm is borrowed from the area of fault tolerant networks and is adapted for the NoC context. We compare this with an algorithm designed using a methodology for design of application specific routing algorithms for communication networks. Our study shows that the application specific routing algorithm not only provides much higher adaptivity, but also superior performance as compared to the other algorithm in all traffic cases.

  • 29. Jain, Sushil
    et al.
    Kumar, Anshul
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Hybrid Multi-FPGA Board Evaluation by permitting limited multi-hop routing2004In: Design automation for embedded systems, ISSN 0929-5585, E-ISSN 1572-8080, Vol. 8, no 4, p. 309-326Article in journal (Refereed)
  • 30. Kommineni, Bhavani Prasad
    et al.
    Srinivasan, Rajkumar
    Holsmark, Rickard
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems.
    Johansson, Alf
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems.
    Modeling and Evaluation of a NoC-Internet Interface2004In: Swedish System on Chip Conference, Båstad, April 13-14, 2004, 2004Conference paper (Other (popular scientific, debate etc.))
    Abstract [en]

    A bridge will be required to interface a multi-core SoC, built using NoC paradigm, to the external world through Internet. In this paper we discuss and compare options for implementation of such a bridge. We have modeled one option in order to study the performance of the bridge with respect to buffer sizes and communication traffic rates. Our study shows that small buffer in the bridge is sufficient to achieve a bandwidth of at least 10 Mbits/s.

  • 31.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Embedded Systems.
    On Packet Switched Networks for On-Chip Communication2003In: Networks on Chip / [ed] Axel Jantsch and Hannu Tenhunen, Boston: Kluwer Academic Publishers , 2003, p. 85-106Chapter in book (Other (popular science, discussion, etc.))
  • 32.
    Kumar, Shashi
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Embedded Systems.
    Jantsch, Axel
    Soininen, J.-P.
    Forsell, M.
    Öberg, J.
    Tiensyrjä, K.
    Hemani, Ahmed
    A Network on Chip Architecture and design Methodology2002In: IEEE Computer Society Annual Symposium on VLSI: New Paradigms for VLSI Systems Design, 2002, p. 117-124Conference paper (Refereed)
  • 33.
    Mejia, Andres
    et al.
    Technical University of Valencia, Spain.
    Palesi, Maurizio
    University of Catania, Italy.
    Flich, José
    Technical University of Valencia, Spain.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems.
    Lopez, Pedro
    Technical University of Valencia, Spain.
    Holsmark, Rickard
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems.
    Duato, José
    Technical University of Valencia, Spain.
    Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs2009In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 17, no 3, p. 356-369Article in journal (Refereed)
    Abstract [en]

    An efficient routing algorithm is important for large on-chip networks [network-on-chip (NoC)] to provide the required communication performance to applications. Implementing NoC using table-based switches provide many advantages, including possibility of changing routing algorithms and fault tolerance, due to the option of table reconfigurations. However, table-based switches have been considered unsuitable for NoCs due to their perceived high area and power consumption. In this paper, we describe the region-based routing (RBR) mechanism which groups destinations into network regions allowing an efficient implementation with logic blocks. RBR can also be viewed as a mechanism to reduce the number of entries in routing tables. RBR is general and can be used in conjunction with any adaptive routing algorithm. In particular, we have evaluated the proposed scheme in conjunction with a general routing algorithm, namely segment-based routing (SR) and an application specific routing algorithm (APSRA) using regular and irregular mesh topologies. Our study shows that the number of entries in the table is significantly reduced, especially for large networks. Evaluation results show that RBR requires only four regions to support several routing algorithms in a 2-D mesh with no performance degradation. Considering link failures, our results indicate that RBR combined with SR is able to tolerate up to 7 link failures in an 8times8 mesh. RBR also reduces area and power dissipation of an equivalent table-based implementation by factors of 8 and 10, respectively. Moreover, the degradation in performance of the network is insignificant when using APSRA combined with RBR.

  • 34.
    Mubeen, Saad
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems.
    Designing Efficient Source Routing for Mesh Topology Network on Chip Platforms2010In: IEEE Euro-Micro Digital System Design 2010, Los Alamitos, California: IEEE Computer Society , 2010Conference paper (Refereed)
    Abstract [en]

    Efficient on-chip communication is very important for exploiting enormous computing power available on a multi-core chip. Network on Chip (NoC) has emerged as a competitive candidate for implementing on-chip communication. Routing algorithms significantly affect the performance of a NoC. Most of the existing NoC architectural proposals advocate distributed routing algorithms for building NoC platforms. Although source routing offers many advantages, researchers avoided it due to its apparent disadvantage of larger header size requirement that results in lower bandwidth utilization. In this paper we make a strong case for the use of source routing for NoCs, especially for platforms with small sizes and regular topologies. We present a methodology to compute application specific efficient paths for communication among cores with a high degree of load balancing. The methodology first selects the most appropriate deadlock free routing algorithm, from a set of routing algorithms, based on the application’s traffic patterns. Then the selected (possibly adaptive) routing algorithm is used to compute efficient static paths with the goal of link load balancing. We demonstrate through simulation based evaluation that source routing has a potential of achieving higher performance, for example up to 28% lower latency even at medium load , as compared to distributed routing.  A simple scheme is proposed for encoding of router ports to reduce the header overhead. A generic simulator was developed for evaluation and performance comparison between source routing and distributed routing. We also designed a router to support source routing for mesh topology NoC platforms.

  • 35. Palesi, Maurizio
    et al.
    Holsmark, Rickard
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems.
    Catania, Vincenzo
    A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems2006In: International Conference on Hardware-Software Codesign and System Synthesis, Seoul, Korea, October 22-25, 2006, 2006Conference paper (Refereed)
    Abstract [en]

    In this paper, we present a methodology to specialize the routing

    algorithm in routing table based NoC routers. It tries to maximize the communication performance while ensuring deadlock free routing for an application. We demonstrate through analysis that routing algorithms generated by our methodology have higher adaptiveness as compared to turn-model based deadlock free routing algorithms for a mesh topology NoC architecture. Performance evaluation is carried out by using a flit-accurate simulator on traffic scenarios generated by both synthetic and real applications. Average delay is considered as performance index for comparison purposes. The routing algorithms generated by the proposed methodology outperforms deterministic and

    adaptive routing algorithms. As compared to deterministic XY routing algorithm and adaptive Odd-Even routing algorithm we observe an improvement in delay close to 50% and 30% on average respectively.

  • 36.
    Palesi, Maurizio
    et al.
    University of Catania, Italy.
    Holsmark, Rickard
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems.
    Catania, Vincenzo
    University of Catania, Italy.
    Application Specific Routing Algorithms for Networks on Chip2009In: IEEE Transactions on Parallel and Distributed Systems, ISSN 1045-9219, E-ISSN 1558-2183, Vol. 20, no 3, p. 316-330Article in journal (Refereed)
    Abstract [en]

    In this paper we present a methodology to develop efficient and deadlock free routing algorithms for Network-on-Chip (NoC) platforms which are specialized for an application or a set of concurrent applications. The proposed methodology, called application specific routing algorithm (APSRA), exploits the application specific information regarding pairs of cores which communicate and other pairs which never communicate in the NoC platform to maximize communication adaptivity and performance. The methodology also exploits the known information regarding concurrency/non-concurrency of communication transactions among cores for the same purpose. We demonstrate, through analysis of adaptivity as well as simulation based evaluation of latency and throughput, that algorithms produced by the proposed methodology give significantly higher performance as compared to other deadlock free algorithms for both homogeneous as well as heterogeneous 2D mesh topology NoC systems. For example, for homogeneous mesh NoC, APSRA results in approximately 30% less average delay as compared to odd-even algorithm just below saturation load. Similarly the saturation load point for APSRA is significantly higher as compared to other adaptive routing algorithms for both homogeneous and non-homogeneous mesh networks.

  • 37. Palesi, Maurizio
    et al.
    Holsmark, Rickard
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Embedded Systems.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Embedded Systems.
    Catania, Vincenzo
    APSRA: A methodology for design of Application Specific Routing Algorithms for NoC Systems2006Report (Other (popular science, discussion, etc.))
    Abstract [en]

    A future NoC architecture must be general enough to allow volume production and must have features to specialize and configure to match and meet application's performance requirements. In this report, we present a methodology to specialize the routing algorithm in NoC routers to optimize its communication performance while ensuring deadlock free routing. Duato's theory of deadlock free routing is extended to incorporate application's communication requirements to

    improve routing adaptiveness. We demonstrate through analysis and modeling and evaluation that routing algorithms produced by our methodology have higher adaptiveness and higher performance as compared to general purpose deadlock free routing algorithms.

  • 38.
    Palesi, Maurizio
    et al.
    DIIT, University of Catania, Italy.
    Holsmark, Rickard
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Wang, X.
    Department of Electrical and Computer Engineering, University of Nevada, Las Vegas, USA.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Yang, M.
    Department of Electrical and Computer Engineering, University of Nevada, Las Vegas, USA.
    Jiang, Y.
    Department of Electrical and Computer Engineering, University of Nevada, Las Vegas, USA.
    Catania, V.
    DIIT, University of Catania, Italy.
    A Novel Mechanism to Guarantee In-Order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip2010In:  13th Euromicro Conference On Digital System Design Architectures, Methods and Tools, 2010Conference paper (Refereed)
    Abstract [en]

    Although adaptive routing algorithms promise higher communication performance, as compared to deterministic routing algorithms, they suffer from the out-of-order packet delivery problem. In the context of Network on Chip, the area and computational overhead of ordering packets at the destination is high and may reverse any gain achieved through the use of adaptivity of the routing algorithm. In this paper, we describe a novel scheme for ensuring in-order packet delivery while retaining the performance advantages of adaptive routing. The hardware architecture of a router that supports the proposed scheme is described. Although the basic idea in our proposal is topology independent we evaluate and compare the performance of our scheme with both deterministic as well as adaptive routing algorithms for 2D mesh NoC. As compared to the XY routing algorithm, our technique significantly reduces the packet delay and improves the saturation point. The impact on router area and power dissipation is also discussed. Although the power consumption of routers increase, the energy consumption per flit increases less than 2% on average, since the higher performance allows for draining more traffic during a certain time window.

  • 39. Palesi, Maurizio
    et al.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems.
    Catania, V.
    Bandwidth-Aware Routing Algorithms for Networks-on-Chip Platforms2009In: I E T Computers and Digital Techniques, ISSN 1751-8601, Vol. 3, no 5, p. 413-429Article in journal (Refereed)
    Abstract [en]

    General purpose routing algorithms for a network-on-chip (NoC) platform may not be able to provide sufficient performance for some communication intensive applications. This may be because of low adaptivity offered by a general purpose routing algorithm resulting in some links getting highly congested. In this study the authors demonstrate that it is possible to design highly efficient application-specific routing algorithms which distribute traffic more uniformly by using information regarding applications communication behaviour (communication topology and communication bandwidth). The authors use off-line analysis to estimate expected load on various links in the network. The result of this analysis is used along with the available routing adaptivity in each router to distribute less traffic to links and paths which are expected to be congested. The methodology for application-specific routing algorithms is extended to incorporate these features to design highly adaptive deadlock-free routing algorithms which also distribute traffic more uniformly and reduce network congestion. The authors discuss architectural implications and analyse area and power overheads of the proposed approach on the design of a table-based NoC router.

  • 40. Palesi, Maurizio
    et al.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems. Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Catania, V.
    Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Network-on-Chip2010In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, ISSN ISSN 0278-0070, Vol. Vol. 29, no 3, p. 426-440Article in journal (Refereed)
    Abstract [en]

    The communication infrastructure of a complex multicore system-on-a-chip is getting an increasing fraction of the overall chip area. According to the International Technology Roadmap for Semiconductors, killer defect density does not decrease over successive technology generations. For this reason, the probability that a manufacturing defect affects the communication system is predicted to increase. In this paper, we deal with manufacturing defects which affect the links in a network on-chip-based interconnection system. The goal of this paper is to show that by using effective routing functions, supported by appropriate selection policies and with a limited amount of extra logic in the router, it is easy to exploit partially faulty links to improve the performance of the system. We show that, instead of discarding partially faulty links, they can be used at reduced capacity to improve the distribution of the traffic over the network, yielding performance and power improvements. We couple an application-specific routing function with a set of selection policies which are aware of link fault distribution and evaluate them on both synthetic traffic and a real complex multimedia application. We also present an implementation of the router, augmented with the extra logic, to support both the proposed selection functions and the transmission of messages over partially faulty links. We analyze the router in terms of silicon area, timing, and power dissipation.

  • 41. Palesi, Maurizio
    et al.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems.
    Holsmark, Rickard
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems.
    A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures2006In: SAMOS VI: Embedded Computer Systems: Architectures, Modeling, and Simulation. Samos, Greece, July 17-20, 2006, 2006Conference paper (Refereed)
    Abstract [en]

    One way to specialize a general purpose multi-core chip built using

    NoC principles is to provide a mechanism to configure an application

    specific deadlock free routing algorithm in the underlying

    communication network. A table in every router, implemented using a

    writable memory, can provide a possibility of specializing the routing

    algorithm according to the application requirements. In such an

    implementation the cost (area) of the router will be proportional to

    the size of the routing table. In this paper, we propose a method to

    compress the routing table to reduce its size such that the resulting

    routing algorithm remains deadlock free as well as has high

    adaptivity. We demonstrate through simulation based evaluation that

    our application specific routing algorithm gives much higher

    performance, in terms of latency and throughput, as compared to

    general purpose algorithms for deadlock free routing. We also show

    that a table size of two entries for each output port gives

    performance within 3\% of the uncompressed table.

  • 42. Palesi, Maurizio
    et al.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems.
    Holsmark, Rickard
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems.
    Catania, Vincenzo
    Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms2007In: Proceedins of 21st Internation Parallel and Distributed Symposium March 26-30, Long Beach, California, USA: 14th Reconfigurable Architectures Workshop, 2007Conference paper (Refereed)
    Abstract [en]

    In this paper we make a case for the use of NoC

    paradigm to develop future FPGAs in which large computational

    blocks (cores) are connected to each other through

    a packet switched communication network. We propose a

    methodology to develop efficient and deadlock free routing

    algorithms for such NoC platforms which can be specialized

    for an application or a set of concurrent applications.

    Application specific topology of communicating cores as

    well as information about their communication concurrency

    over time is exploited to maximize communication adaptivity

    and performance. We demonstrate, both through analysis

    of adaptivity as well as simulation based evaluation

    of latency and throughput, that our algorithm gives significantly

    higher performance as compared to general purpose

    deadlock free algorithms like XY and Odd-Even.

  • 43. Palesi, Maurizio
    et al.
    Longo, G.
    Signorino, S.
    Holsmark, Rickard
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Data-Och Electronik. Jönköping University, School of Engineering, JTH. Research area Embedded Systems.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Data-Och Electronik. Jönköping University, School of Engineering, JTH. Research area Embedded Systems.
    Catania, V.
    Design of bandwidth aware and congestion avoiding efficient routing algorithms for Network on Chip platforms2008In: The 2nd IEEE International Symposium on Networks-on-Chip: Symposium on Networks-on-Chip (NOCS 2008), 2008, p. 97-106Conference paper (Refereed)
  • 44.
    Pop, Ruxandra
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Embedded Systems.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Embedded Systems.
    Mapping Applications to NoC Platforms with Multithreaded Processor Resources2005In: Proceedings of 23rd Norchip Conference, November 2005., 2005Conference paper (Refereed)
  • 45.
    Pop, Ruxandra
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Embedded Systems.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Embedded Systems.
    On performance Improvement of Concurrent Applications using Simultaneous Multithreaded Processors as NoC resources2006In: Proceedings of NORCHIP 2006, 2006, p. 191-196Conference paper (Refereed)
  • 46.
    Samuelsson, Henrik
    et al.
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Embedded Systems.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Embedded Systems.
    Ring Road NoC Architecture2004In: Proceedings of NORCHIP 2004, 2004Conference paper (Other (popular scientific, debate etc.))
  • 47. Tornero, Rafael
    et al.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems.
    Mubeen, Saad
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Distance Constrained Mapping to Support NoC Platforms based on Source Routing2009In: 3rd Highly Parallel Processing on Chip (HPPC 09) workshop, August 2009, Delft, Netherland. / [ed] Martti Forsell and Jesper Larsson Träff, 2009, p. 8-17Conference paper (Refereed)
  • 48.
    Ubar, Raimund
    et al.
    Tallinn Technical University.
    Brik, Marina
    Tallinn Technical University.
    Jutman, Artur
    Tallinn Technical University.
    Raik, Jaan
    Tallinn Technical University.
    Bengtsson, Tomas
    Tallinn Technical University.
    Kumar, Shashi
    Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
    Functional Test Generation for Finite State Machines2006In: BEC 2006 : 2006 International Baltic Electronics Conference: proceedings of the 10th biennial Baltic Electronics Conference : Tallinn University of Technology, October 2-4, 2006, Tallinn, Estonia, 2006, p. 205-208Conference paper (Refereed)
1 - 48 of 48
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