Network-on-Chip (NoC) is a new on-chip communication paradigm for future IP-core based System-on-Chip (SoC), designed to remove a number of limitations of today’s on-chip interconnect solutions. A NoC interconnects cores by means of a packet switched micro-network, which improves scalability and reusability, resulting in a shorter time to market. A typical NoC will be running many applications concurrently, which results in shared network capacity between different kinds of traffic flows. Due to the diverse characteristic of applications, some traffic flows will require real-time communication guarantees while others are tolerant to even some loss of data. In order to provide different levels of Quality-of-Service (QoS) for traffic flows, the communication traffic is separated into different service classes. Traffic in NoC is typically classified into two service classes: the guaranteed throughput (GT) and the best-effort (BE) service class. The GT class offers strict QoS guarantees by setting up a virtual path with reserved bandwidth between the source (GT-producer) and destination (GT-consumer), called a GT-path. The BE class offers no strict QoS guarantees, but tries to efficiently use any network capacity which may become available from the GT traffic. The GT traffic may not fully utilize its bandwidth reservation if its communication volume varies, leading to time intervals where there is no GT traffic using the bandwidth reservation. These intervals are referred to as slack-time. If the slack can not be used this leads to unnecessarily reduced performance of BE traffic, since a part of the available network capacity becomes blocked. This thesis deals with methods to efficiently use the slack-time for BE traffic. The contributions include three new dynamic schemes for slack distribution in NoC. First, a scheme to inform the routers of a GT-path about available slack is evaluated. The GT-producer plans its traffic using a special playout buffer, and issues control packets containing the actual amount of slack-time available. The results show that this scheme leads to decreased latency, jitter and packet drops for BE traffic. Secondly, an extension to this scheme is evaluated, where slack is distributed among multiple GT-paths (slack distribution in space). This opens up the possibility to balance the QoS of BE traffic flows which overlap with the GT-paths. Thirdly, a scheme to distribute slack among the links of a GT-path (slack distribution in time) is proposed. In this approach, arriving GT-packets, at a certain router along the GT-path, can wait for a maximum defined amount of time. During this time, any waiting BE traffic in the buffers can be forwarded over the GT-path. The results confirm that this is especially important during high BE-traffic load, where this technique decreases the jitter of BE traffic considerably.

The induced current in a wire placed inside a conducting box due to field penetration through apertures has been studied using FDTD simulations. Two box configurations have been investigated in order to evaluate the difference in coupling with one large aperture and the combination of a large and a narrow aperture. The coupling to a wire placed above a ground plane has also been studied to compare it with the test cases involving the box.

A CFD-aided reflow oven profile prediction algorithm has been developed and applied to modelling of preheating of a PCB with non-uniform distribution of component thermal mass in a forced air convection solder reflow oven. The iterative algorithm combines an analytic approach with CFD modelling. It requires an experimentally validated CFD model of the solder reflow oven and a CFD model of the PCB as main inputs. Results of computational experiments have been presented to reveal good agreement between predicted PCB profiles and corresponding CFD calculations. Application guidelines contained in the description of the algorithm will assist potential users both during the virtual prototyping phase of a PCB including designing for assembly and in the phase of reflow oven profiling.

Humidity management of commercial-of-the-shelf electronic components in non-controlled climatic environments can be realized e.g. by introducing a local printed circuit board heater. By choosing appropriate size and location of the heater plate in the vicinity of the critical electronic packages, and utilizing logic control function, it is possible to improve the quality of local humidity management and reduce power consumption of the heater, which is important especially in case of battery driven portable or vehicle mounted devices. A computational fluid dynamics assisted methodology has been developed to determine the best feasible design of the heater, followed by experimental verification of the constructed logic controlled heater. The experiment has been performed in a harsh climatic environment including temperature variation from +33°C to +40°C, and relative humidity variation from 54% to 80%. Analysis of the experimental %RH and temperature curves as well as power profile of the heater has confirmed the feasibility of the chosen approach to maintain greater than 9°C difference between the electronics package surface temperature and the local dew point temperature, by applying discrete power pulses with the amplitude less than 6 W.

A CFD modelling methodology including experimental validation has been developed and applied for investigation of anti-moisture measures in a non- hermetic electronics enclosure containing a number of printed circuit boards, and placed in a severe storage environment. In the climatic test the temperature and the relative humidity have been varried from +33degC to +71degC and from 14% to 80%, respectively. Enclosure heater solutions have been parametrically studied by simulation. A heating strategy involving various power levels has been determined, which is just sufficient to maintain the internal relative humidity below 60%, thereby reducing the risk for dew formation on the electronics assembly.

Different block and tube mounting alternatives for SiC-based gas sensors were studied by means of temperature measurements and simulation of heat transfer and gas flow for steady state conditions. The most preferable tube mounting design was determined. Simulation-based guidelines were developed for designing tube-mounted gas sensors in the exhaust pipes of diesel and petrol engines, taking into account thermal constraints and flow conditions.

Simulation-based guidelines were developed for designing tube-mounted gas sensors in the exhaust pipes of diesel and petrol engines, taking into account thermal constraints and gas flow conditions. Different block and tube mounting alternatives for SiC-based gas sensors were studied by means of temperature measurements and simulation of steady state heat transfer and gas flow. Design variables included the number of fins in the heat sink mounted on the inlet tube, the inlet construction, the mounting tube orientation, and the micro-heater substrate placement inside the mounting tube. The most preferable tube mounting design was determined with respect to the thermal performance of the sensor structure and with respect to the gas flow parameters, which are important for the sensor's selectivity, sensitivity and response time.

Test of electronic circuits for fabrication fault is important if the circuits should have reasonable quality. To make the development of complex circuits manageable, methods and computer tools that work on a high level of abstraction are required. Development of test methodologies have however been left behind the increase of abstraction level used for the design. There is a risk that testing aspects become a bottle neck in the development of complex circuits if the test methods fail to cope up with the abstraction level for the design methods.

System on Chips is often used to implement complex systems. The methods to make test for those circuits consists of three main parts. First part is the development of test procedures for the cores, which is preferably made at high level of abstraction. This area includes fault modeling and test pattern generation at behavior level of abstraction or higher as well as design of extra logic for insertion to facilitate testing. The second part requires development of methods to test the interconnections among cores.

The third part is to develop a test access mechanism which can be used to test the cores and interconnections within a SoC. This survey is about development of fault models and test pattern for testing of cores at higher level of abstraction than logic level. A promising architecture for the interconnection is the Network on Chip architecture in which cores are interconnected through a network of packet switched switches. Testing of these switches will be identical to testing of a core.

Models of physical and fabrication faults are needed at higher levels of abstraction in order to be able to develop test patterns from functional or behavioral description of cores. Researchers have experienced that the stuck-at fault model works quite well at logic level. But no such fault model has been discovered at behavioral or higher level which is universally accepted. Several behavior level fault models have been proposed. One of the proposed models is the variable bit stuck-at fault model. This model has been derived from the logic level stuck-at fault model but it does not give adequate coverage of physical faults. Physical faults inside components, like arithmetic and logic units, cannot be modeled in this way. With the methods proposed so far, knowledge of the logic level implementation of the unit is needed to model such faults. In this survey, we describe three proposed classes of fault models - fault models derived from logic level stuck-at faults, operator mutation faults and physically induced faults.

Testing at higher level of abstraction has a lot in common with software testing. The pattern generation methods can be classified into two main categories, namely, code oriented methods and fault oriented methods. Methods can also be classified into methods that use fault simulation for test pattern generation or use algorithmic approach for test pattern generation. These two classification approaches are orthogonal leading to four different categories of methods. We have tried to put existing approaches in this category. We also survey the experimental setups developed and used by various research groups for carrying out research in high level testing. Some very interesting conclusions can be drawn about the efficacy of various categories of test pattern generation methodologies for testing various types of systems at behavioral level. An interesting conclusion is that code oriented methods are not very effective for testing data dominated circuits at behavioral level.

Approaches followed by five different research groups working in the area of high level testing is also summarized and compared. We feel that the hierarchical test pattern generation method, which works simultaneously on several levels of abstraction, to generate test patterns is the most promising of these methods. We also feel that new fault models need to be developed to make testing at higher level of abstraction achieve adequate coverage of physical faults and become practically useful.

Purpose – The paper seeks, by means of measurement and modelling, to evaluate frequency dependent per-unit-length parameters of conductive textile transmission line (CTTL) for wearable applications and to study deterioration of these parameters when CTTL is subjected to washing.

Design/methodology/approach – The studied transmission line is made of Nickel/Copper (Ni/Cu) plated polyester ripstop fabric and is subjected to standard 60°C cycle in a commercial off-the-shelf washing machine. The per-unit-length parameters (resistance and inductance) and characteristic impedance of the line are extracted from measurements before and after washing. Using the measurement data an equivalent circuit is created to model the degradation of the line. The circuit is then integrated in a three-dimensional transmission line matrix (TLM) model of the transmission line.

Findings – Both an electrical equivalent circuit and a TLM model are developed describing the degradation of the conductive textile when washed. A severe deterioration of the electrical parameters of the line is noticed. Experimental and modelling results are in good agreement in the addressed frequency band.

Research limitations/implications – Analysis is performed for frequencies up to 10?MHz. The developed TLM model can be used to conduct parametric studies of the CTTL. To counteract the degradation of the line, protective coating is to be considered in further studies.

Originality/value – This paper extends knowledge of the subject by experimental and simulation-based characterization of the CTTL when subjected to washing cycles.

By means of statistical modelling and measurement, the triboelectric current noise spectral density is evaluated for shielded cables in body-borne wired network subjected to mechanical stresses. Assuming a shot noise model, an expression for the current spectral density of the noise is derived. The efficiency of the methodology is demonstrated by measuring the triboelectric current noise in two shielded cables subjected to bending. Thereafter the parameters of the noise pulses' waiting time and amplitude probability density functions are extracted from measurement, thus enabling the computation of the current spectral density of the noise induced mechanically in body-borne wired networks.

An active inductor based on an improved gyrator circuit is proposed. The active inductor is developed to be implemented in a high impedance transceiver for a wearable DC power line communication network where requirements such as low power consumption, high bandwidth and numerous nodes support are prioritized. A load isolation step is introduced to ensure the stability of the active inductance's size on different load currents. The proposed gyrator circuit is analyzed and optimized by means of theoretical calculations. The theoretical results are then verified by simulations and experiments in the frequency range up to 10 MHz.

Wearable systems put high demands on wearability and robustness. Conductive fabrics are very likely to be used in wearable systems due to their textile-like characteristics. However conductive fabrics must be able to resist environmental stresses (wearing, laundering, etc.) in the same way as clothing in order to fully comply with the requirements.

A demonstrator, TxWear, was constructed to exploit conductive fabrics in building a conductive textile transmission line for intermodular communication and power transmission (DC power line communication bus), thus eliminating the need for cables between the modules. The hardware modules are connected to the conductive line through connectors from textile industry, i.e., snap fasteners. Different types of conductive fabrics (Ni/Cu plated polyester fabrics and stainless-steel based elastic ribbon) were evaluated and compared according to their conductivity, flexibility and robustness characteristics. The effect of washing on the electrical properties (per-unit-length parameters) of the textile transmission line was studied. Different coating processes, i.e., parylene and silicone coating, were studied and evaluated in order to isolate and enhance the robustness of the conductive textile. Ni/Cu plated polyester ripstop fabric was found to be not appropriate for wearable applications, while conductive elastic ribbon showed good robustness to laundry induced stresses.

Precision processing in MOEMS (micro-opto-electromechanical systems) packaging has been studied based on electrochemical processes with the purpose of establishing technology for low-cost multifunctional encapsulation of microsystems and assembly of opto-electric access links in polymer.

The electrochemically based processes studied in this paper include:

1.Electroforming of a polymer moulding tool (stamper) in a nickel sulphamate electrolyte on a high-precision 3D etched silicon template.

2.Patterning of 3D surfaces by an electrophoretic photoresist.

3.Precision plating of Au and Sn for self-alignment of chips by eutectic Au–Sn solder.

The results show that nickel stampers with adequately low internal stress can be electroformed on 3D silicon wafers. Furthermore, 3D polymer samples manufactured by the nickel stampers can be patterned with metal lines down to 20 μm width using electrophoretic photoresist. Finally, eutectic Au–Sn solder bumps are realized by electroplating of Au and Sn followed by reflowing, satisfying the demands on dimension and alloy composition control over a 4 in. Si wafer.