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Junction Based Routing: A Scalable Technique To Support Source Routing in Large NoC Platforms
Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. (Emedded Systems)
Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. (Emedded Systems)
Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. (Embedded Systems)
2012 (English)In: Proceedings of Network on Chip Architectures 2012, ACM Digital Library, 2012, 45-50 p.Conference paper, Published paper (Refereed)
Abstract [en]

To support communication among hundreds of cores on a chip, on-chip communication must be well organized. In the embedded systems using such a chip, the communication patterns can be profiled off-line and routing can be well planned. Source routing has been shown to be suitable in such contexts. However, source routing has one serious drawback of overhead for storing the path information in header of every packet. This disadvantage becomes worse as the size of the network grows. In this paper we propose a technique, called Junction Based Routing (JBR), to remove this limitation. In the proposed technique, path information for only a few hops is stored in the packet header.

With this information, either the packet reaches the destination, or  reaches a junction from where the path information for on-ward path is picked up. There are many interesting issues related to this approach. We discuss and solve two important issues related to JBR, namely, the required number of junctions and their positions and path computation for efficient deadlock-free routing. A simulator has been developed to evaluate the performance of JBR and compare it with simple source routing. We observe that JBR has slightly worse performance as compared to pure source routing for packets with large payload. But JBR has  potential of higher performance for packets with small payloads.

Place, publisher, year, edition, pages
2012. 45-50 p.
Keyword [en]
Network on Chip, Source Routing, Deadlock Free Routing, Junction, Router Architecture
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:hj:diva-20283DOI: 10.1145/2401716.2401727ISBN: 978-1-4503-1540-1 (print)OAI: oai:DiVA.org:hj-20283DiVA: diva2:589510
Conference
Fifth International Workshop on Network on Chip Architectures (NoCArc 2012), 1st Dec. 2012, Vancouver, BC, Canada
Available from: 2013-01-18 Created: 2013-01-18 Last updated: 2013-01-21Bibliographically approved

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
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Language
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