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Processor evaluation cube: A classification and survey of processor evaluation techniques
Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems.
Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems.
2004 (English)Report (Other academic)
Abstract [en]

Selecting appropriate hardware resources corresponding to the application is an important task for design of an embedded system or a SoC. A large number of techniques have been proposed in literature to select a processor matching with the application requirements. In this report, we propose a framework called Processor Evaluation Cube (PEC) which helps in systematic classification and comparison of various processor evaluation techniques. The three axes of PEC are: Analysis, Architecture and Abstraction. The Analysis axis distinguishes methods employing static analysis or simulation; Architecture axis distinguishes methods evaluating single processor or multiprocessor computing platforms; Abstraction axis distinguishes methods employing clock true evaluation or higher level execution time estimation techniques. Our survey not only puts the existing techniques in proper perspective but also points to the weaknesses in the existing techniques which need to be removed if these techniques have to be used for design of multi-processor SoC (System on Chip) and Network on Chip (NoC) systems. We observe during our survey that the techniques for single processor evaluation are getting adapted for evaluation of multiprocessor platforms. We also note that there are no techniques developed or proposed for low level static analysis of multi-processor platforms due to complexity of such an evaluation. Although many different evaluation approaches may fall in the same category in PEC classification they have significant differences in intermediate descriptions of application, architecture and performance parameters.

Place, publisher, year, edition, pages
Jönköping: Ingenjörshögskolan , 2004. , p. 17
Series
Research Report. School of Engineering, ISSN 1404-0018 ; 2004:3
Keywords [en]
Processor architectures, Performance, Evaluation, Estimation, Simulation, Multi-processor, Systems on Chip
Identifiers
URN: urn:nbn:se:hj:diva-43OAI: oai:DiVA.org:hj-43DiVA, id: diva2:4143
Available from: 2004-12-02 Created: 2004-12-02 Last updated: 2011-09-29Bibliographically approved

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Holsmark, RickardKumar, Shashi

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
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  • vancouver
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More styles
Language
  • de-DE
  • en-GB
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Output format
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