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Off-line Testing of Delay Faults in NoC Interconnects
Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
Tallinn Technical University.
Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
Tallinn Technical University.
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2006 (Swedish)In: Proceedings: 9th EUROMICRO Conference on Digital System Design : architectures, methods, and tools : (DSD 2006), 30 August-1 September 2006, Cavtat near Dubrovnik, Crotia, 2006, p. 677-680Conference paper, Published paper (Refereed)
Abstract [en]

Testing of high density SoCs operating at high clock speeds is an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when the chip works at normal operating speed. In this paper, we propose a methodology for at-speed testing of delay faults in links connecting two distinct clock domains in a SoC. We give an analytical analysis about the efficiency of this method. We also propose a simple digital hardware structure for the receiver end of the link under test to detect delay faults. It is possible to extend our method to combine it with functional testing of the link and adapt it for online testing

Place, publisher, year, edition, pages
2006. p. 677-680
Identifiers
URN: urn:nbn:se:hj:diva-6446DOI: 10.1109/DSD.2006.72ISBN: 0-7695-2609-8 (print)OAI: oai:DiVA.org:hj-6446DiVA, id: diva2:37266
Available from: 2007-08-02 Created: 2007-08-02 Last updated: 2011-08-10Bibliographically approved

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Bengtsson, TomasKumar, Shashi

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