In this paper we make a case for the use of NoC

paradigm to develop future FPGAs in which large computational

blocks (cores) are connected to each other through

a packet switched communication network. We propose a

methodology to develop efficient and deadlock free routing

algorithms for such NoC platforms which can be specialized

for an application or a set of concurrent applications.

Application specific topology of communicating cores as

well as information about their communication concurrency

over time is exploited to maximize communication adaptivity

and performance. We demonstrate, both through analysis

of adaptivity as well as simulation based evaluation

of latency and throughput, that our algorithm gives significantly

higher performance as compared to general purpose

deadlock free algorithms like XY and Odd-Even.