One way to specialize a general purpose multi-core chip built using

NoC principles is to provide a mechanism to configure an application

specific deadlock free routing algorithm in the underlying

communication network. A table in every router, implemented using a

writable memory, can provide a possibility of specializing the routing

algorithm according to the application requirements. In such an

implementation the cost (area) of the router will be proportional to

the size of the routing table. In this paper, we propose a method to

compress the routing table to reduce its size such that the resulting

routing algorithm remains deadlock free as well as has high

adaptivity. We demonstrate through simulation based evaluation that

our application specific routing algorithm gives much higher

performance, in terms of latency and throughput, as compared to

general purpose algorithms for deadlock free routing. We also show

that a table size of two entries for each output port gives

performance within 3\% of the uncompressed table.