Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
On Connecting Cores to Packet Switched On-Chip Networks: A Case Study with MicroBlaze Processor Cores
Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems. (Inbyggda System)
Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems. (Inbyggda System)
Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. JTH. Research area Embedded Systems. (Inbyggda System)
2004 (English)In: 7th IEEE Workshop DDECS 04, Slovakia, 18-21 April, 2004, 2004Conference paper, Published paper (Refereed)
Abstract [en]

The idea of using on chip packet switched networks for interconnecting a large number of IP cores is very practical for designing complex SoCs since it gives possibility of not only reusing IP cores but also the interconnection infrastructure. However, the real effort and time in using these Networks on Chip (NoC) goes in developing interfaces for connecting cores to the on-chip network. Standardization of interfaces for these cores can speed up the development process. In this paper, we present our work of developing an interface for a standard bus called OPB to the on-chip network. Any cores having OPB as the wrapper can reuse this interface. The paper also describes implementation of a small NoC prototype using this idea on an FPGA platform. The performance measurements on the prototype not only demonstrate the feasibility of NoC implementation but also demonstrate that FPGA based NoC implementation will be able to meet the performance requirements in many application areas. Specifically, we show that a core can communicate 2.5 MPackets/sec to a neighboring core.

Place, publisher, year, edition, pages
2004.
National Category
Information Systems
Identifiers
URN: urn:nbn:se:hj:diva-4048ISBN: 80-969117-9-1 (print)OAI: oai:DiVA.org:hj-4048DiVA, id: diva2:34868
Available from: 2007-08-02 Created: 2007-08-02 Last updated: 2018-01-12

Open Access in DiVA

No full text in DiVA

Authority records BETA

Holsmark, RickardJohansson, AlfKumar, Shashi

Search in DiVA

By author/editor
Holsmark, RickardJohansson, AlfKumar, Shashi
By organisation
JTH, Computer and Electrical EngineeringJTH. Research area Embedded Systems
Information Systems

Search outside of DiVA

GoogleGoogle Scholar

isbn
urn-nbn

Altmetric score

isbn
urn-nbn
Total: 166 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf