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Designing Efficient Source Routing for Mesh Topology Network on Chip Platforms
Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems.
Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems.
2010 (English)In: IEEE Euro-Micro Digital System Design 2010, Los Alamitos, California: IEEE Computer Society , 2010Conference paper, (Refereed)
Abstract [en]

Efficient on-chip communication is very important for exploiting enormous computing power available on a multi-core chip. Network on Chip (NoC) has emerged as a competitive candidate for implementing on-chip communication. Routing algorithms significantly affect the performance of a NoC. Most of the existing NoC architectural proposals advocate distributed routing algorithms for building NoC platforms. Although source routing offers many advantages, researchers avoided it due to its apparent disadvantage of larger header size requirement that results in lower bandwidth utilization. In this paper we make a strong case for the use of source routing for NoCs, especially for platforms with small sizes and regular topologies. We present a methodology to compute application specific efficient paths for communication among cores with a high degree of load balancing. The methodology first selects the most appropriate deadlock free routing algorithm, from a set of routing algorithms, based on the application’s traffic patterns. Then the selected (possibly adaptive) routing algorithm is used to compute efficient static paths with the goal of link load balancing. We demonstrate through simulation based evaluation that source routing has a potential of achieving higher performance, for example up to 28% lower latency even at medium load , as compared to distributed routing.  A simple scheme is proposed for encoding of router ports to reduce the header overhead. A generic simulator was developed for evaluation and performance comparison between source routing and distributed routing. We also designed a router to support source routing for mesh topology NoC platforms.

Place, publisher, year, edition, pages
Los Alamitos, California: IEEE Computer Society , 2010.
Keyword [en]
Network on Chip (NoC); Distributed Routing; Source Routing; Routing Algorithms; Performance Analysis
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:hj:diva-12358OAI: oai:DiVA.org:hj-12358DiVA: diva2:321738
Conference
IEEE Euro-Micro Digital System Design 2010
Note
The conference will be held in Sept. 2010 in FranceAvailable from: 2010-06-02 Created: 2010-06-02 Last updated: 2010-09-09Bibliographically approved

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CiteExportLink to record
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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
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Output format
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