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Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Network-on-Chip
Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems. Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
2010 (English)In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, ISSN ISSN 0278-0070, Vol. Vol. 29, no 3, p. 426-440Article in journal (Refereed) Published
Abstract [en]

The communication infrastructure of a complex multicore system-on-a-chip is getting an increasing fraction of the overall chip area. According to the International Technology Roadmap for Semiconductors, killer defect density does not decrease over successive technology generations. For this reason, the probability that a manufacturing defect affects the communication system is predicted to increase. In this paper, we deal with manufacturing defects which affect the links in a network on-chip-based interconnection system. The goal of this paper is to show that by using effective routing functions, supported by appropriate selection policies and with a limited amount of extra logic in the router, it is easy to exploit partially faulty links to improve the performance of the system. We show that, instead of discarding partially faulty links, they can be used at reduced capacity to improve the distribution of the traffic over the network, yielding performance and power improvements. We couple an application-specific routing function with a set of selection policies which are aware of link fault distribution and evaluate them on both synthetic traffic and a real complex multimedia application. We also present an implementation of the router, augmented with the extra logic, to support both the proposed selection functions and the transmission of messages over partially faulty links. We analyze the router in terms of silicon area, timing, and power dissipation.

Place, publisher, year, edition, pages
IEEE Publisher , 2010. Vol. Vol. 29, no 3, p. 426-440
Keywords [en]
Application Specific routing, congestion, fault tolerance, network-on-chip, performance analysis, router design, routing algorithm
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:hj:diva-11582DOI: 10.1109/TCAD.2010.2041851OAI: oai:DiVA.org:hj-11582DiVA, id: diva2:292336
Available from: 2010-02-05 Created: 2010-02-05 Last updated: 2017-12-12Bibliographically approved

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Kumar, Shashi

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JTH. Research area Robust Embedded SystemsJTH, Computer and Electrical Engineering
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