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Power and Energy Efficiency Evaluation for HW and SW Implementation of nxn Matrix Multiplication on Altera FPGAs
Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. (Abdelghani Renbi, Lennart Lindh)
2009 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

In addition to the performance, low power design became an important issue in the design process of mobile embedded systems. Mobile electronics with rich features most often involve complex computation and intensive processing, which result in short battery lifetime and particularly when low power design is not taken in consideration. In addition to mobile computers, thermal design is also calling for low power techniques to avoid components overheat especially with VLSI technology. Low power design has traced a new era. In this thesis we examined several techniques to achieve low power design for FPGAs, ASICs and Processors where ASICs were more flexible to exploit the HW oriented techniques for low power consumption. We surveyed several power estimation methodologies where all of them were prone to at least one disadvantage. We also compared and analyzed the power and energy consumption in three different designs, which perform matrix multiplication within Altera platform and using state-of-the-art FPGA device. We concluded that NIOS II\e is not an energy efficient alternative to multiply nxn matrices compared to HW matrix multipliers on FPGAs and configware is an enormous potential to reduce the energy consumption costs.

Place, publisher, year, edition, pages
2009. , 101 p.
Keyword [en]
Low Power Design Techniques, Energy Efficiency, FPGA, ASIC, SoC, NIOS, CMOS, Power Estimation, Latency, Matrix Multiplication, Configware, Reconfigurable Computing, RISC
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering Information Science Information Science Computer Engineering Computer Science
Identifiers
URN: urn:nbn:se:hj:diva-10545OAI: oai:DiVA.org:hj-10545DiVA: diva2:242166
Presentation
2009-09-25, E3231, Gjuterigatan 5, Jönköping University, 13:00 (English)
Uppsok
Technology
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Examiners
Available from: 2009-10-12 Created: 2009-10-07 Last updated: 2009-10-12Bibliographically approved

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CiteExportLink to record
Permanent link

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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf