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Power and Energy Efficiency Evaluation for HW and SW Implementation of nxn Matrix Multiplication on Altera FPGAs
Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering.
Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. Jönköping University, School of Engineering, JTH. Research area Robust Embedded Systems.
2009 (English)In: 6th FPGAWORLD September 10, 2009, Stockholm, Sweden. ACM, 2009Conference paper, (Refereed)
Abstract [en]

Matrix multiplication is most often involved in graphics, image processing, digital signal processing, robotics and control engineering applications. In this paper we compared and analyzed the power and energy consumption in three different designs, which multiply two matrices A and B of nxn 32-bit items and store the result in C matrix of nxn 64-bit items. The first two designs use FPGA HW with different number of storage registers 2n and 2n2 and the third design uses a computer system piloted by NIOS II\e processor with On-Chip memory. We showed that NIOS II\e is not an energy efficient alternative to multiply nxn matrices compared to HW matrix multiplier on FPGA.

Since our target FPGA is the Altera cyclone II family, we also had to find one acceptable method to measure the real power consumption in the FPGA device.

Place, publisher, year, edition, pages
2009.
Identifiers
URN: urn:nbn:se:hj:diva-10531OAI: oai:DiVA.org:hj-10531DiVA: diva2:241888
Available from: 2009-10-08 Created: 2009-10-06 Last updated: 2010-02-03Bibliographically approved

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Renbi, AbdelghaniLindh, Lennart
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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
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More styles
Language
  • de-DE
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  • nn-NB
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  • Other locale
More languages
Output format
  • html
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