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A Multi-Level Routing Scheme and Router Architecture to support Hierarchical Routing in Large Network on Chip Platforms
Högskolan i Jönköping, Tekniska Högskolan, JTH, Data- och elektroteknik. (Inbyggda System)
Högskolan i Jönköping, Tekniska Högskolan, JTH, Data- och elektroteknik. (Inbyggda System)
DIIT,University of Catania, Italy.
2010 (engelsk)Inngår i: 4th Workshop on Highly Parallel Processing on a Chip (HPPC 2010), 2010Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

The concept of hierarchical networks is useful for designing a large heterogeneous NoC by reusing predesigned small NoCs as subnets. It can also be helpful when analyzing and designing a large NoC as interconnection of subnets at a higher level of abstraction. Hierarchical deadlock-free routing is required to enable deadlock-free interconnection of sub-networks with different internal routing algorithms. In this paper we show that multi-level addressing is a cost-effective implementation option for hierarchical deadlock-free routing. We propose a two-level routing scheme, which is not only efficient, but also  enables co-existence of algorithmic and table-based implementation in one router. A hierarchical view of the network simplifies addressing of network nodes and address decoding in the router. Synthesis results show that a 2-level hierarchical router design for an 8x8 NoC, can reduce area and power requirements by  up to ~20%, as compared to a router for the flat network. This work also proposes a new possibility for increasing the number of nodes available for subnet-to-subnet interfaces, while keeping the properties of hierarchical deadlock-freedom. We evaluate and discuss the communication performance in a 2-level hierarchical network for various subnet interface set-ups and traffic situations. A cycle accurate simulator has been developed and used for this purpose.

sted, utgiver, år, opplag, sider
2010.
Emneord [en]
Networks on Chip, Hierarchical Networks, Deadlock Free Routing, Router Architecture
HSV kategori
Identifikatorer
URN: urn:nbn:se:hj:diva-13124OAI: oai:DiVA.org:hj-13124DiVA, id: diva2:351370
Konferanse
4th Workshop on Highly Parallel Processing on a Chip (HPPC 2010)
Tilgjengelig fra: 2010-09-17 Laget: 2010-09-14 Sist oppdatert: 2018-01-12bibliografisk kontrollert

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