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EVALUATION OF SOURCE ROUTING FOR MESH TOPOLOGY NETWORK ON CHIP PLATFORMS
Jönköping University, School of Engineering, JTH, Computer and Electrical Engineering. (Network on Chip)
2009 (English)Independent thesis Advanced level (degree of Master (Two Years)), 80 credits / 120 HE creditsStudent thesis
Abstract [en]

Network on Chip is a scalable and flexible communication infrastructure for the design of core based System on Chip. Communication performance of a NoC depends heavily on the routing algorithm. Deterministic and adaptive distributed routing algorithms have been advocated in all the current NoC architectural proposals. In this thesis we make a case for the use of source routing for NoCs, especially for regular topologies like mesh. The advantages of source routing include in-order packet delivery; faster and simpler router design; and possibility of mixing non-minimal paths in a mainly minimal routing. We propose a method to compute paths for various communications in such a way that traffic congestion is avoided while ensuring deadlock free routing. We also propose an efficient scheme to encode the paths.

We developed a tool in Matlab that computes paths for source routing for both general and application specific communications. Depending upon the type of traffic, this tool computes paths for source routing by selecting best routing algorithm out of many routing algorithms. The tool uses a constructive path improvement algorithm to compute paths that give more uniform link load distribution. It also generates different types of traffics. We also developed a simulator capable of simulating source routing for mesh topology NoC. The experiments and simulations which we performed were successful and the results show that the advantages of source routing especially lower packet latency more than compensate its disadvantages. The results also demonstrate that source routing can be a good routing candidate for practical core based SoCs design using network on chip communication infrastructure.

Place, publisher, year, edition, pages
2009. , p. 117
Keywords [en]
Network on Chip (NoC), System on Chip (SoC), Core Based Design, On Chip Communication, Distributed Routing, Source Routing, Routing Algorithms, Performance Analysis, Packet Switched Network, Specification and Description Language (SDL)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering Other Electrical Engineering, Electronic Engineering, Information Engineering Computer Engineering
Identifiers
URN: urn:nbn:se:hj:diva-9591OAI: oai:DiVA.org:hj-9591DiVA, id: diva2:224758
Presentation
2009-06-16, E-1405, School of Engineering, Jönköping, 10:00 (English)
Uppsok
teknik
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Examiners
Available from: 2009-06-23 Created: 2009-06-22 Last updated: 2018-01-13Bibliographically approved

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CiteExportLink to record
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Citation style
  • apa
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