Testing of high density SoCs operating at high clock speeds is an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when the chip works at normal operating speed. In this paper, we propose a methodology for at-speed testing of delay faults in links connecting two distinct clock domains in a SoC. We give an analytical analysis about the efficiency of this method. We also propose a simple digital hardware structure for the receiver end of the link under test to detect delay faults. It is possible to extend our method to combine it with functional testing of the link and adapt it for online testing

Test of electronic circuits for fabrication fault is important if the circuits should have reasonable quality. To make the development of complex circuits manageable, methods and computer tools that work on a high level of abstraction are required. Development of test methodologies have however been left behind the increase of abstraction level used for the design. There is a risk that testing aspects become a bottle neck in the development of complex circuits if the test methods fail to cope up with the abstraction level for the design methods.

System on Chips is often used to implement complex systems. The methods to make test for those circuits consists of three main parts. First part is the development of test procedures for the cores, which is preferably made at high level of abstraction. This area includes fault modeling and test pattern generation at behavior level of abstraction or higher as well as design of extra logic for insertion to facilitate testing. The second part requires development of methods to test the interconnections among cores.

The third part is to develop a test access mechanism which can be used to test the cores and interconnections within a SoC. This survey is about development of fault models and test pattern for testing of cores at higher level of abstraction than logic level. A promising architecture for the interconnection is the Network on Chip architecture in which cores are interconnected through a network of packet switched switches. Testing of these switches will be identical to testing of a core.

Models of physical and fabrication faults are needed at higher levels of abstraction in order to be able to develop test patterns from functional or behavioral description of cores. Researchers have experienced that the stuck-at fault model works quite well at logic level. But no such fault model has been discovered at behavioral or higher level which is universally accepted. Several behavior level fault models have been proposed. One of the proposed models is the variable bit stuck-at fault model. This model has been derived from the logic level stuck-at fault model but it does not give adequate coverage of physical faults. Physical faults inside components, like arithmetic and logic units, cannot be modeled in this way. With the methods proposed so far, knowledge of the logic level implementation of the unit is needed to model such faults. In this survey, we describe three proposed classes of fault models - fault models derived from logic level stuck-at faults, operator mutation faults and physically induced faults.

Testing at higher level of abstraction has a lot in common with software testing. The pattern generation methods can be classified into two main categories, namely, code oriented methods and fault oriented methods. Methods can also be classified into methods that use fault simulation for test pattern generation or use algorithmic approach for test pattern generation. These two classification approaches are orthogonal leading to four different categories of methods. We have tried to put existing approaches in this category. We also survey the experimental setups developed and used by various research groups for carrying out research in high level testing. Some very interesting conclusions can be drawn about the efficacy of various categories of test pattern generation methodologies for testing various types of systems at behavioral level. An interesting conclusion is that code oriented methods are not very effective for testing data dominated circuits at behavioral level.

Approaches followed by five different research groups working in the area of high level testing is also summarized and compared. We feel that the hierarchical test pattern generation method, which works simultaneously on several levels of abstraction, to generate test patterns is the most promising of these methods. We also feel that new fault models need to be developed to make testing at higher level of abstraction achieve adequate coverage of physical faults and become practically useful.